"ECC" describes four genuinely different things depending on what carries it: plain non-ECC (no error correction at all), ECC UDIMM (error correction on an unbuffered module), registered ECC (error correction combined with an RDIMM's register buffer), and DDR5's on-die ECC (automatic per-chip correction inside the DRAM package itself, which sits alongside - not in place of - the module's own system-level ECC bits, per Lenovo Press documentation).
Updated · vendor documents read 14-16 September 2026
A non-ECC module carries only data bits - no extra circuitry to detect or correct a bit flip. Lenovo Press's own DDR5 documentation states the comparison directly: "Non-ECC DIMMs have only the 32 data bits per channel, and will only be used in end-user devices." That last clause is doing real work: it positions non-ECC as the consumer-desktop default, not something a server platform's own memory documentation typically lists as a supported option.
An ECC UDIMM adds the extra correction bits to an otherwise unbuffered module - the signal path from controller to DRAM stays direct, exactly as on a plain UDIMM, with correction bits layered on top. It solves the data-integrity problem without solving the electrical-load problem an RDIMM's register buffer addresses, which is why it shows up mainly on entry-level towers and workstations rather than on high-density rack servers. See our RDIMM vs UDIMM page for the buffering distinction on its own.
Most rack and tower servers specify RDIMM that also carries ECC - the register chip that buffers command/address signals, combined with the extra correction bits, on one module. This is the class Samsung's own current DDR5 RDIMM lineup lists at up to 256GB per module, and it is what the phrase "registered ECC" is normally shorthand for on a server spec sheet.
Lenovo Press describes DDR5's on-die mechanism directly: "DDR5 introduces an automatic on-die single-bit error correction (SEC) that fixes possible errors before outputting data to the controller. Error correction continues to the system level, where each DDR5 channel consists of 32 data bits and 8 ECC (error checking and correction) bits."
Read carefully, that passage describes two separate correction points inside the same channel, not one replacing the other: on-die SEC corrects errors inside the DRAM chip itself, before the data ever leaves the package, while the module's own 8 ECC bits per 32 data bits correct errors that can occur afterward - in transmission across the channel to the controller. A DDR5 module still has to be an ECC-class module (ECC UDIMM or registered ECC) for that second, system-level layer to exist at all; on-die correction is present on DDR5 more broadly and does not by itself make a non-ECC DDR5 module equivalent to an ECC one. We have not found a vendor source that states this using the words "not a substitute" specifically, so we are describing the mechanism as documented rather than attributing that phrase to Lenovo or anyone else.
Read the module's own printed label or the listing's stated specification first - "ECC," "Registered," and "Unbuffered" are normally spelled out directly rather than left for a buyer to infer. Where a part number is all that's available, manufacturer-specific grammar can confirm it independently: Micron encodes ECC via a 72-bit data width segment in its own part-numbering scheme, which is how our part-number pages verify RAM listings without guessing. See also our how-to-check-installed-memory page for reading back what is physically installed on a running system.
Which ECC class (if any) your specific server requires is set by the platform, not by this page. See our OEM-verified platform pages for models we have checked directly, or the manufacturer's own memory-configuration guide for anything we have not yet built.
Cheapest in-stock ECC UDIMM and registered (RDIMM/LRDIMM) modules right now, computed live.
| Class | Brand | Module | Capacity | $/GB | |
|---|---|---|---|---|---|
| RDIMM | SK Hynix | HMAA8GL7MMR4N | 64GB | $4.61 | Buy Now |
| RDIMM | A-Tech | M393A2G40DB0-CPB | 16GB | $5.44 | Buy Now |
| RDIMM | Samsung | M393A8K40B22-CWD | 64GB | $6.23 | Buy Now |
| LRDIMM | Supermicro | B07DFLTWN3 | 64GB | $6.23 | Buy Now |
| RDIMM | Samsung | M393A2G40EB1-CPB | 16GB | $7.12 | Buy Now |
| RDIMM | MICRON | MTA36ASF4G72PZ | 32GB | $7.19 | Buy Now |
Non-ECC memory carries only data bits and cannot detect or correct a bit flip. Lenovo Press states the DDR5 comparison directly: "Non-ECC DIMMs have only the 32 data bits per channel, and will only be used in end-user devices." ECC memory adds extra bits specifically to detect, and in most cases correct, single-bit errors before they corrupt data the system relies on.
No - they answer different questions. ECC UDIMM adds error-correction bits to an otherwise unbuffered module; it does not add the register buffer chip that defines an RDIMM. A server that requires registered memory will not accept ECC UDIMM as a substitute - see our RDIMM vs UDIMM page for the buffering distinction itself.
It describes an RDIMM that also carries ECC - the register buffer chip (which reduces electrical load on the memory controller, letting more ranks share a channel) plus the extra ECC bits for error correction, combined on one module. This is the default class most rack and tower servers specify, distinct from a UDIMM that happens to also carry ECC.
No - on-die ECC and system-level (registered) ECC are not the same layer, and one is not a substitute for the other. Lenovo Press describes DDR5's on-die correction as fixing "possible errors before outputting data to the controller," after which "error correction continues to the system level, where each DDR5 channel consists of 32 data bits and 8 ECC... bits." That is two separate correction points in the same channel, not one mechanism replacing the other - a DDR5 module still needs to be an ECC-class module (ECC UDIMM or registered ECC) for the system-level correction Lenovo describes to exist at all.
As documented, yes for this generation's automatic per-chip single-bit correction - Lenovo Press specifically introduces it as a DDR5 feature. We have not sourced an equivalent DDR4 on-die mechanism from any vendor this session, so we are not claiming DDR4 has one.
Read the module's own label or the listing's stated specification - "ECC" is normally spelled out directly, and our own part-number decoder confirms it independently on the major brands we track (Micron, for example, encodes ECC via a 72-bit data width in its part-numbering grammar). Never assume ECC from a server chassis alone; check the module itself.
Specification claims on this page were checked against the pages below on 16 September 2026. Where a widely-repeated figure did not survive that check, we report what the source says now and say so in the text rather than repeating the familiar number.